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preliminary publication release date: april 21, 2005 - 1 - revision 1.0 wms7130/1 nonvolatile digital potentiometers with up/down (3-wire) interface, 10kohm, 50kohm, 100kohm resistance 32 taps with optional output buffer
wms7130/1 - 2 - 1. general description the wms713x is a 32 non-volatile linear digital potentiometers available in 10k ? , 50k ? and 100k ? resistance values. the wms7130/1 can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. the output of each potentiometer is determined by the wiper position, which varies in linearly between v a and v b terminal according to the content stored in the volatile tap register (tr) which is programmed through up/down (increment/decrement ) interface. the channel has one non-volatile memory location (nvmem0) that can be directly wri tten to by users through the up/down interface. power-on recall is also built in so the content of t he nvmem0 to tap register is automatically loaded. the wms7130/1 devices pin out the resistor wiper directly. the wms7131 devices feature an output buffer with 3ma minimum drive capability. all the wms7130/1 devices are si ngle channel devices offered in 8-pin pdip, soic and msop packages. the wms7130/1 devices operate over a wide operating voltage ranging from 2.7v to 5.5v. 2. features ? drop-in replacements for many popular parts ? available output buffer for wms7131 devices ? single linear-taper channel ? 32 taps ? 10k, 50k and 100k end-to end resistance ? v ss to v dd terminal voltages ? non-volatile storage of wiper positions with power-on recall ? data storage and potentiometer control through up/down (3-wire) interface ? endurance 100,000 write cycles ? data retention 100 years ? package options: o 8-pin pdip, soic or msop ? industrial temperature range: -40 ~ 85c ? single supply operation 2.7v to 5.5v
wms7130/1 publication release date: april 21, 2005 - 3 - revision 1.1 up/down serial interface tap register decode r nvmem0 nv memory nv memory control cs v ss v dd v a v b v w inc u/d up/down serial interface tap register decode r nvmem0 nv memory nv memory control cs v ss v dd v a v b v w inc u/d 3. block diagram figure 1 ? wms7130 block diagram (rheostat mode) figure 2 ? wms7131 block diagram (divider mode)
wms7130/1 - 4 - 4. table of contents 1. general d escription......................................................................................................... ......... 2 2. features .................................................................................................................... ..................... 2 3. block diagram ............................................................................................................... ............... 3 4. table of cont ents ........................................................................................................... ........... 4 5. pin conf igurati on ........................................................................................................... ............ 5 6. pin des cription ............................................................................................................. ................ 6 7. functional descript ion...................................................................................................... ...... 7 7.1. potentiomete r and rheosta t modes .......................................................................................... ... 7 7.1.1. rheostat configur ation .................................................................................................. ........ 7 7.1.2. potentiomete r configur ation ............................................................................................. ..... 7 7.2. non-volatile memory (nvmem) ............................................................................................... .... 7 7.3. serial da ta inte rface ..................................................................................................... ................ 8 7.4. operati on over view ........................................................................................................ .............. 8 8. timing diagrams............................................................................................................. ............... 9 9. absolute maxi mum ratings.................................................................................................... 11 10. electrical cha racteris tics ............................................................................................... 12 10.1 test circui ts ............................................................................................................. .................. 14 11. typical applic ation ci rcuits .............................................................................................. 1 5 11.1. layout c onsiderat ions .................................................................................................... .......... 17 12. package drawings and dimens ions.................................................................................. 18 13. ordering informat ion....................................................................................................... .... 21 14. version history ............................................................................................................ ........... 22
wms7130/1 publication release date: april 21, 2005 - 5 - revision 1.1 5. pin configuration 1 v ss 1 2 3 4 5 6 7 8 2 3 45 6 7 8 1 2 3 45 6 7 8 inc v dd u/d v a cs v b v w v ss v w v w 8-msop 8-soic 8-pdip inc u/d v a v dd cs v b v ss inc u/d v a v dd cs v b
wms7130/1 - 6 - 6. pin description table 1 ? pin description pin name i/o description inc i increment control. a high-low transition of inc when cs is low will move the wiper up or down for one increment based on the u/ d input u/ d i up/down control input. high state will cause the wiper to move to the v b terminal, low state to the v a terminal v a - high terminal of winpot v ss - ground pin, logic ground reference v dd - power supply cs i chip select. when cs is high, the part is deselected and the device will be in the standby mode. cs low enables the part, placing it in the active power mode v b - low terminal of winpot v w o wiper terminal of winpot (can be buffered), its position on the resistor array is controlled by the inputs on inc , u/ d , and cs
wms7130/1 publication release date: april 21, 2005 - 7 - revision 1.1 7. functional description the wms7130/1, a nonvolatile digitally programmable potentiometers with 32 taps, with or without output buffer, is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. the chip can store up to one 8-bit word in a nonvol atile memory (nvmem0) in order to set the tap register value when the device is powered up. the wms7130/1 is controlled by a serial up-down (3-wire) interface that allows setting the tap register value as well as storing data in the nonvolatile memory. 7.1. p otentiometer and r heostat m odes the wms7130/1 can operate as either a rheostat or as a potentiometer (voltage divider). when in the potentiometer configuration there are two po ssible modes. one is done using wms7130 winpot device without the output buffer and the other m ode is done with wms7131 winpot device with the output buffer. 7.1.1. rheostat configuration the wms7130/1 acts as a two terminal resistive element in the rheostat configuration where one terminal can be connected to either t he end point pins of the resistor (v a and v b ) and the other terminal is the wiper (v w ) pin. this configuration controls the resistance between the two terminals and the resistance can be adjusted by sending t he corresponding tap register setting to the wms7130/1 or can also be set by loading a pre-se t tap register value from nonvolatile memory nvmem0 upon power up. 7.1.2. potentiometer configuration in potentiometer configuration an input voltage is applied to either one of the end point pins (v a or v b ). the voltage on the wiper pin will be proportional to the voltage difference between v a and v b and the wiper setting. the resistance cannot be dire ctly measured in this configuration. 7.2. n on -v olatile m emory (nvmem) the wms7130/1 has one nvmem position available for storing the potentiometer setting. the nvmem position can be directly written via the up /down interface. the potentiometer is loaded with the value stored in the nvmem0 on power up.
wms7130/1 - 8 - 7.3. s erial d ata i nterface the up/down family has a 3-wire serial data interface consisting of cs , inc , u/ d pins. only up/down operations can be performed. the ke y features of this interface include: ? increment/decrement operations on the tap register (tr) ? direct refresh of tap register (tr) from internal nvmem ? nonvolatile storage of the present tap register value into the nvmem and automatic recall at power up ? for wms7131 devices, output buffer amplifier 7.4. o peration o verview the wiper position or the tap register(tr) setting can only be changed by the up/down operation with the combination of cs , u/ d , and inc signals. when cs is low, the part will be activated and the tr setting can be changed by toggling inc , and tr will move up when u/ d is high and move down when u/ d is low. the tr setting will be stored into the user nvmem automatically each time cs goes high while inc holds high. otherwise, if inc is low when cs goes high, the tr setting will not be stored. the nvmem content will be automat ically loaded into tr at power on. the user nvmem can be tested through the voltage measurement on the wiper pin after saving tr setting into the nvmem and reloading into the tr. when the tr setting is already at low, further down operations won?t change the setting. similarly, when tr setting is at high, further up operations won?t change the setting. when cs is held high, the part will be in standby mode and the tr setting will not be changed. the operating modes of up/down are summarized below. cs u/ d inc operation low high high to low wiper toward v a low low high to low wiper toward v b low to high x high store wiper position low to high x low no store, return to standby high x x standby note: x means don?t care
wms7130/1 publication release date: april 21, 2005 - 9 - revision 1.1 8. timing diagrams conditions: v dd = +2.7v to 5.5v, v a = v dd , v b = 0v, t = 25 c figure 3 ?wms7130/1 timing diagram note: [1] mi in the ac timing diagram (figure 3) refers to the mi nimum incremental change in the wiper output due to a change in the wiper position. u /d cs inc t i l t d i t i d t i h t c yc t c i t i c t f t r v w mi [1] 90% 90% 1 0% ( store ) t c ph t i w
wms7130/1 - 10 - table 10 ? timing parameters parameters symbol min. max. units cs to inc setup t ci 100 ns u/ d to inc setup t di 50 ns u/ d to inc hold t id 100 ns inc low period t il 250 ns inc high period t ih 250 ns inc inactive to cs inactive t ic 1 s cs deselect time (no store) t cph 100 ns cs deselect time (store) t cph 15 (2.7v) ms inc to v w change t iw 5 s inc cycle time t cyc 1 s inc input rise and fall time t r , t f 500 s power-up to wiper stable t pu 1 ms v cc power-up rate t r v cc 0.2 (13ms 0-2.7v) 50 (54 s 0-2.7v) v/ms
wms7130/1 publication release date: april 21, 2005 - 11 - revision 1.1 9. absolute maximum ratings table 11 ? absolute maximum ratings (packaged parts) [1] conditions values junction temperature 150oc storage temperature -65o to +150oc voltage applied to any pad (v ss ? 0.3v) to (v dd + 0.3v) v dd ? v ss -0.3 to 7.0v table 12 ? operating conditions (packaged parts) conditions values commercial operating temperature range 0oc to +70oc extended operating temperature -20oc to +70oc industrial operating temperature -40oc to +85oc supply voltage (v dd ) +2.7v to +5.5v ground voltage (v ss ) 0v [1] stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functiona l operation is not implied at these conditions
wms7130/1 - 12 - 10. electrical characteristics table 12 ? electrical characteristics (packaged parts) parameters symbol min. typ. max. units conditionds rheostat mode nominal resistance r -20 +20 % t=25oc, v w open different non linearity [2] dnl -1 +1 lsb integral non linearity [2] inl -1 +1 lsb tempo 1 ? r ab / ? t 300 ppm/ c wiper resistance [2] r w 50 ? v dd =5v, i=v dd /r total 80 ? v dd =2.7v, i=v dd /r total wiper current i w -1 1 ma divider mode resolution n 8 bits different non linearity [2] dnl -1 0.4 +1 lsb integral non linearity [2] inl -1 0.4 +1 lsb temperature coefficient [1] ? v w / ? t +20 ppm/ c code = 80h full scale error v fse -1 0 lsb code = full scale zero scale error v zse 0 1 lsb code = zero scale resistor terminal voltage range v a ,v b ,v w v ss v dd v terminal capacitance [1] c a , c b 30 pf wiper capacitance [1] 30 pf dynamic characteristics [1] bw 10k 1.5 mhz v dd =5v, v b =vss bandwidth ?3db bw 50k 300 khz code = 80h bw 100k 200 khz settling time to 1 lsb t s 80 100 us analog output (buffer enables) amp output current i out 3 ma v o =1/2 scale amp output resistance rout 1 10 ? i l = 100ua total harmonic distortion [1] thd 0.08 % v a =2.5v, v dd =5v, f=1khz, v in =1v rms digital inputs/outputs input high voltage v ih 0.7v dd v input low voltage v il 0.3v dd v
wms7130/1 publication release date: april 21, 2005 - 13 - revision 1.1 parameters symbol min. typ. max. units conditionds output low voltage v ol 0.4 v i ol =2ma input leakage current i li -1 +1 ua cs =v dd ,vin=vss ~ v dd output leakage current i lo -1 +1 ua cs =v dd ,vin=v ss ~ v dd input capacitance [1] c in 25 pf v dd =5v, fc = 1mhz output capacitance [1] c out 25 pf v dd =5v, fc = 1mhz power requirements operating voltage v dd 2.7 5.5 v operating current i ddr 0.5 1 ma all ops except nvmem program operating current i ddw 1 2 ma during non-volatile memory program i sa [3] 0.5 1 ma buffer is active, nop, no load standby current i sb [4] 0.1 1 ua buffer is inactive, power down, no load power supply rejection ratio psrr 1 lsb/v v dd =5v 10%, code=80h notes: [1] not subject to production test. [2] lsb = (v a - v b ) / (t- 1); dnl = (v i+1 - v i ) / lsb; inl = (v i - i*lsb) / lsb; where i = [0, (t -1)] and t = # of taps of the device. [3] wms71x1 only. [4] wms71x0 only.
wms7130/1 - 14 - 10.1 t est c ircuits figure 4 ? test circuits potentiometer divider nonlinearit y error test circuit ( inl, dnl ) *assume infinite in p ut im p edance v+ v ms * v+ = v dd 1lsb= v+/256 wms71xx v a v b v w resistor p osition nonlinearit y error test circuit (rheostat operation: r-inl, r-dnl) *assume infinite in p ut im p edance no connection v ms * wms71xx w v a v b v w i w wms71xx wi p er resistance test circuit *assume infinite in p ut im p edance v ms * wms71xx v a v b v w i w i w = v dd /r total r w = v ms /i w power supply sensitivity te st circuit (pss, psrr) *assume infinite in p ut im p edance v + v + = v dd 10% v a v b v w v ms * psrr ( db ) = 20log ( ) ? v ms ? v dd pss ( %/% ) = ? v ms ? v dd wms71xx v a v b v w v in ~ +5v 2.5v dc offset v out ca p acitance test circuit v a v b wms71xx v w v in ~ +5v 2.5v dc v out offset gnd gain vs . fre q uenc y test circuit
wms7130/1 publication release date: april 21, 2005 - 15 - revision 1.1 11. typical application circuits vin v out = - v in a b r r r a = 256 d) (256 r ab ? , r b = 256 d r ab r ab = total resistance of potentiometer d = wiper setting for wms71xx figure 5 ? programmable inverting gain amplifier using the wms7130/1 v out = v in (1+ a b r r ) r a = 256 d) (256 r ab ? , r b = 256 d r ab r ab = total resistance of potentiometer d = wiper setting for wms71xx figure 6 ? programmable non-inverting gain amplifier using the wms7130/1 op a mp _ v out wms71xx + op a mp v in v out wms71xx _ r a r b r a r b +
wms7130/1 - 16 - figure 7 ? wms7130/1 tri mming voltage reference figure 8 ? wms7130/1 rf amp control v refh wms71xx v+ gnd v ref = 5.0v i = 32ma filter l1 choke wms71xx winpot cs\ u/d\ inc\ v ss v a v w v b v dd rf input rf out vdd q1 rf power amp c1 0.1uf c2 cs\ inc\ u/d\
wms7130/1 publication release date: april 21, 2005 - 17 - revision 1.1 11.1. l ayout c onsiderations use a 0.1 f bypass capacitor as close as possible to the v dd pin. this is recommended for best performance. often this can be done by placing the surface mount capacitor on the bottom side of the pc board, directly between the v dd and v ss pins. care should be taken to separate the analog and digital traces. sensitive traces should not run under the device or close to the bypass capacitors. a dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. cap v dd cs v b v w inc u/d v a v ss analog signal lines digital control lines analog signal line digital control line figure 9 ? wms7130/1 layout
wms7130/1 - 18 - 12. package drawings and dimensions l o c d a1 a e b seating plane y 0.25 gauge plane e h e 1 8 5 4 4.00 0.25 0.51 0.25 e c b a1 3.80 0.19 0.33 0.10 0.157 0.010 0.020 0.010 0.150 0.008 0.013 0.004 max. dimension in mm 1.75 a symbol min. 1.35 dimension in inch 0.069 min. 0.053 max. control demensions are in milmeters . 1.27 0.10 6.20 l y h 010 0.40 5.80 e 1.27 bsc 0.050 0.004 0.244 0 0.016 0.228 10 0.050 bsc e d 4.80 5.00 0.188 0.196 figure 10: 8l 150mil soic
wms7130/1 publication release date: april 21, 2005 - 19 - revision 1.1 1.63 1.47 0.064 0.058 symbol min nom max max nom min dim ension in inch dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 0.360 0.380 9.14 9.65 0 15 0.045 1.14 0.355 0.335 8.51 9.02 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 8 5 1 4 figure 11: 8l 300mil pdip
wms7130/1 - 20 - figure 12: 8l 3mm msop
wms7130/1 publication release date: april 21, 2005 - 21 - revision 1.1 13. ordering information winbond?s winpot part number description: output buffer end-to-end resistance soic pdip msop 10k wms7130 010s wms7130 010p wms7130 010m 50k wms7130 050s wms7130 050p wms7130 050m no 100k wms7130 100s wms7130 100p wms7130 100m 10k wms7131 010s wms7131 010p wms7131 010m 50k wms7131 050s wms7131 050p wms7131 050m yes 100k wms7131 100s wms7131 100p wms7131 100m for the latest product information, access winbond?s worldwide website at http://www.wi nbond-usa.com t b rrr p winbond winpot products w/ up-down interface number of taps: 3 = 32 wms71 for up/down interface: 0 : no buffer 1 : with buffer end-to-end resistance: 010: 10kohm 050: 50kohm 100: 100kohm package: s: soic p: pdip m: msop
wms7130/1 - 22 - 14. version history version date description 1.0 june 2003 initial issue 1.1 april 2005 revise disclaim section
wms7130/1 publication release date: april 21, 2005 - 23 - revision 1.1 headquarters winbond electronics corporation america winbond electronics (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.wi nbond-usa.com/ http:// www.wi nbond.com.tw/ taipei office winbond electronics corporat ion japan winbond electronics (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. this product incorporates superflash? technology licensed from sst. winbond products are not designed, int ended, authorized or warranted for us e as components in systems or equipment intended for surgical implantati on, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control inst ruments, or for other applications intended to support or sustain life. furthermore, winbond pr oducts are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the contents of this document are provided only as a guide for the applications of winbond products. winbond makes no representation or warranties with respect to t he accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. no license, whether express or implied, to any intellect ual property or other right of winbond or others is granted by this publication. except as se t forth in winbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any ex press or implied warranty of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are provided ?as is?, and winbond assumes no liability whatsoever and disclaims any express or implied warranty of merc hantability, fitness for a particular purpos e or infringement of any intellectual property. in no event, shall winbond be liable for any damages whatsoever (including, wi thout limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if winbond has been advis ed of the possibility of such damages. application examples and alternative us es of any integrated circuit contained in this publication are for illustration only and winbond makes no representation or warranty that such applications sha ll be suitable for the use specified. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the winbond reliability report, and are neither warrant ed nor guaranteed by winbond. this product incorporates superflash ? . this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistenc ies exist between the information in this and other product documentation, or in the event that other product documentat ion contains information in addition to the information in this, the information contained herein supersedes and governs such other information in it s entirety. this datasheet is subject to change without notice. copyright ? 2005, winbond electronics corporation. all rights reserved. chipcorder ? and isd ? are trademarks of winbond electronics corporation. superflash ? is the trademark of silicon st orage technology, inc. all other trademarks are p ro p erties of their res p ective owners.

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